Intel

Intel is seeking a Defect Metrology Technician to join its Yield/Defect Metrology department in Phoenix, Arizona.

Intel is seeking a Chemical Mechanical Planarization (CMP) Process Development Engineer to join their Logic Technology Development (LTD) organization in Hillsboro, Oregon.

Intel is seeking a Power Delivery Design Engineer to join their GPE team in Toronto, Canada.

Intel is seeking a Substrate Supply Commodity Manager to oversee the planning and execution of substrate sourcing operations.

Intel is looking for a Source-to-Pay Solutions Senior Lead based in Bangalore, India.

Intel is seeking a Senior Compiler Engineer to join its Compiler Engineering team within the Data Center Group in Shanghai.

Intel is seeking a Senior Compiler Performance Engineer to join its Compiler Engineering team within the Data Center Group in Shanghai.

Intel is seeking a Senior Substrate Engineer to enhance substrate manufacturing technologies within their Asia Capex Substrate Integration group.

Intel is seeking a Senior Process Integration Engineer to enhance substrate manufacturing technologies and streamline integration processes for advanced packaging solutions.

Intel is seeking a Remote Operations Center Manufacturing Technician for its Advanced Packaging Command Center in Penang, Malaysia.

Intel is seeking a CPU Power Delivery Engineer to contribute to high-performance computing by focusing on the physical design implementation of advanced CPU designs.

Intel is looking for a system software engineering intern to join their Linux Core OS Validation team in Gdansk, Poland.

Intel is seeking a Microarchitecture and Design Engineer for its AI SoC organization, which focuses on developing advanced products for various AI applications.

Intel is seeking a GPU Software Development Engineer to join their Graphics validation team in Bangalore, India.

Intel is seeking a Defect Review Technician to join its Advanced Packaging Command Center in Penang, Malaysia.

Intel is seeking a CPU Physical Design Engineer in Bangalore, India, to focus on the physical design implementation of CPU architectures from RTL to GDS.